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Xv6 with picoc & Linkage editor
v1.0
The project delineate mutual cohesion between c library, linkage editor ( linker), interpreter and operating system by porting the same on xv6 kernel
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Xv6 with picoc & Linkage editor
v1.0
The project delineate mutual cohesion between c library, linkage editor ( linker), interpreter and operating system by porting the same on xv6 kernel
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00001 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic. 00002 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 00003 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 00004 00005 This file is part of the GNU C Library. 00006 00007 The GNU C Library is free software; you can redistribute it and/or 00008 modify it under the terms of the GNU Lesser General Public 00009 License as published by the Free Software Foundation; either 00010 version 2.1 of the License, or (at your option) any later version. 00011 00012 The GNU C Library is distributed in the hope that it will be useful, 00013 but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00015 Lesser General Public License for more details. 00016 00017 You should have received a copy of the GNU Lesser General Public 00018 License along with the GNU C Library; if not, write to the Free 00019 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 00020 02111-1307 USA. */ 00021 00022 /* You have to define the following before including this file: 00023 00024 UWtype -- An unsigned type, default type for operations (typically a "word") 00025 UHWtype -- An unsigned type, at least half the size of UWtype. 00026 UDWtype -- An unsigned type, at least twice as large a UWtype 00027 W_TYPE_SIZE -- size in bits of UWtype 00028 00029 UQItype -- Unsigned 8 bit type. 00030 SItype, USItype -- Signed and unsigned 32 bit types. 00031 DItype, UDItype -- Signed and unsigned 64 bit types. 00032 00033 On a 32 bit machine UWtype should typically be USItype; 00034 on a 64 bit machine, UWtype should typically be UDItype. */ 00035 00036 #define __BITS4 (W_TYPE_SIZE / 4) 00037 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) 00038 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) 00039 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) 00040 00041 #ifndef W_TYPE_SIZE 00042 #define W_TYPE_SIZE 32 00043 #define UWtype USItype 00044 #define UHWtype USItype 00045 #define UDWtype UDItype 00046 #endif 00047 00048 /* Define auxiliary asm macros. 00049 00050 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two 00051 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype 00052 word product in HIGH_PROD and LOW_PROD. 00053 00054 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a 00055 UDWtype product. This is just a variant of umul_ppmm. 00056 00057 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 00058 denominator) divides a UDWtype, composed by the UWtype integers 00059 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient 00060 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less 00061 than DENOMINATOR for correct operation. If, in addition, the most 00062 significant bit of DENOMINATOR must be 1, then the pre-processor symbol 00063 UDIV_NEEDS_NORMALIZATION is defined to 1. 00064 00065 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 00066 denominator). Like udiv_qrnnd but the numbers are signed. The quotient 00067 is rounded towards 0. 00068 00069 5) count_leading_zeros(count, x) counts the number of zero-bits from the 00070 msb to the first nonzero bit in the UWtype X. This is the number of 00071 steps X needs to be shifted left to set the msb. Undefined for X == 0, 00072 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value. 00073 00074 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts 00075 from the least significant end. 00076 00077 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, 00078 high_addend_2, low_addend_2) adds two UWtype integers, composed by 00079 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2 00080 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow 00081 (i.e. carry out) is not stored anywhere, and is lost. 00082 00083 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend, 00084 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers, 00085 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and 00086 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE 00087 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, 00088 and is lost. 00089 00090 If any of these macros are left undefined for a particular CPU, 00091 C macros are used. */ 00092 00093 /* The CPUs come in alphabetical order below. 00094 00095 Please add support for more CPUs here, or improve the current support 00096 for the CPUs below! 00097 (E.g. WE32100, IBM360.) */ 00098 00099 #if defined (__GNUC__) && !defined (NO_ASM) 00100 00101 /* We sometimes need to clobber "cc" with gcc2, but that would not be 00102 understood by gcc1. Use cpp to avoid major code duplication. */ 00103 #if __GNUC__ < 2 00104 #define __CLOBBER_CC 00105 #define __AND_CLOBBER_CC 00106 #else /* __GNUC__ >= 2 */ 00107 #define __CLOBBER_CC : "cc" 00108 #define __AND_CLOBBER_CC , "cc" 00109 #endif /* __GNUC__ < 2 */ 00110 00111 #if defined (__alpha) && W_TYPE_SIZE == 64 00112 #define umul_ppmm(ph, pl, m0, m1) \ 00113 do { \ 00114 UDItype __m0 = (m0), __m1 = (m1); \ 00115 (ph) = __builtin_alpha_umulh (__m0, __m1); \ 00116 (pl) = __m0 * __m1; \ 00117 } while (0) 00118 #define UMUL_TIME 46 00119 #ifndef LONGLONG_STANDALONE 00120 #define udiv_qrnnd(q, r, n1, n0, d) \ 00121 do { UDItype __r; \ 00122 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ 00123 (r) = __r; \ 00124 } while (0) 00125 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); 00126 #define UDIV_TIME 220 00127 #endif /* LONGLONG_STANDALONE */ 00128 #ifdef __alpha_cix__ 00129 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X)) 00130 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X)) 00131 #define COUNT_LEADING_ZEROS_0 64 00132 #else 00133 #define count_leading_zeros(COUNT,X) \ 00134 do { \ 00135 UDItype __xr = (X), __t, __a; \ 00136 __t = __builtin_alpha_cmpbge (0, __xr); \ 00137 __a = __clz_tab[__t ^ 0xff] - 1; \ 00138 __t = __builtin_alpha_extbl (__xr, __a); \ 00139 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \ 00140 } while (0) 00141 #define count_trailing_zeros(COUNT,X) \ 00142 do { \ 00143 UDItype __xr = (X), __t, __a; \ 00144 __t = __builtin_alpha_cmpbge (0, __xr); \ 00145 __t = ~__t & -~__t; \ 00146 __a = ((__t & 0xCC) != 0) * 2; \ 00147 __a += ((__t & 0xF0) != 0) * 4; \ 00148 __a += ((__t & 0xAA) != 0); \ 00149 __t = __builtin_alpha_extbl (__xr, __a); \ 00150 __a <<= 3; \ 00151 __t &= -__t; \ 00152 __a += ((__t & 0xCC) != 0) * 2; \ 00153 __a += ((__t & 0xF0) != 0) * 4; \ 00154 __a += ((__t & 0xAA) != 0); \ 00155 (COUNT) = __a; \ 00156 } while (0) 00157 #endif /* __alpha_cix__ */ 00158 #endif /* __alpha */ 00159 00160 #if defined (__arc__) && W_TYPE_SIZE == 32 00161 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00162 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ 00163 : "=r" ((USItype) (sh)), \ 00164 "=&r" ((USItype) (sl)) \ 00165 : "%r" ((USItype) (ah)), \ 00166 "rIJ" ((USItype) (bh)), \ 00167 "%r" ((USItype) (al)), \ 00168 "rIJ" ((USItype) (bl))) 00169 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00170 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ 00171 : "=r" ((USItype) (sh)), \ 00172 "=&r" ((USItype) (sl)) \ 00173 : "r" ((USItype) (ah)), \ 00174 "rIJ" ((USItype) (bh)), \ 00175 "r" ((USItype) (al)), \ 00176 "rIJ" ((USItype) (bl))) 00177 /* Call libgcc routine. */ 00178 #define umul_ppmm(w1, w0, u, v) \ 00179 do { \ 00180 DWunion __w; \ 00181 __w.ll = __umulsidi3 (u, v); \ 00182 w1 = __w.s.high; \ 00183 w0 = __w.s.low; \ 00184 } while (0) 00185 #define __umulsidi3 __umulsidi3 00186 UDItype __umulsidi3 (USItype, USItype); 00187 #endif 00188 00189 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32 00190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00191 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ 00192 : "=r" ((USItype) (sh)), \ 00193 "=&r" ((USItype) (sl)) \ 00194 : "%r" ((USItype) (ah)), \ 00195 "rI" ((USItype) (bh)), \ 00196 "%r" ((USItype) (al)), \ 00197 "rI" ((USItype) (bl)) __CLOBBER_CC) 00198 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00199 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ 00200 : "=r" ((USItype) (sh)), \ 00201 "=&r" ((USItype) (sl)) \ 00202 : "r" ((USItype) (ah)), \ 00203 "rI" ((USItype) (bh)), \ 00204 "r" ((USItype) (al)), \ 00205 "rI" ((USItype) (bl)) __CLOBBER_CC) 00206 #define umul_ppmm(xh, xl, a, b) \ 00207 {register USItype __t0, __t1, __t2; \ 00208 __asm__ ("%@ Inlined umul_ppmm\n" \ 00209 " mov %2, %5, lsr #16\n" \ 00210 " mov %0, %6, lsr #16\n" \ 00211 " bic %3, %5, %2, lsl #16\n" \ 00212 " bic %4, %6, %0, lsl #16\n" \ 00213 " mul %1, %3, %4\n" \ 00214 " mul %4, %2, %4\n" \ 00215 " mul %3, %0, %3\n" \ 00216 " mul %0, %2, %0\n" \ 00217 " adds %3, %4, %3\n" \ 00218 " addcs %0, %0, #65536\n" \ 00219 " adds %1, %1, %3, lsl #16\n" \ 00220 " adc %0, %0, %3, lsr #16" \ 00221 : "=&r" ((USItype) (xh)), \ 00222 "=r" ((USItype) (xl)), \ 00223 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 00224 : "r" ((USItype) (a)), \ 00225 "r" ((USItype) (b)) __CLOBBER_CC );} 00226 #define UMUL_TIME 20 00227 #define UDIV_TIME 100 00228 #endif /* __arm__ */ 00229 00230 #if defined(__arm__) 00231 /* Let gcc decide how best to implement count_leading_zeros. */ 00232 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X)) 00233 #define COUNT_LEADING_ZEROS_0 32 00234 #endif 00235 00236 #if defined (__CRIS__) && __CRIS_arch_version >= 3 00237 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X)) 00238 #if __CRIS_arch_version >= 8 00239 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X)) 00240 #endif 00241 #endif /* __CRIS__ */ 00242 00243 #if defined (__hppa) && W_TYPE_SIZE == 32 00244 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00245 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ 00246 : "=r" ((USItype) (sh)), \ 00247 "=&r" ((USItype) (sl)) \ 00248 : "%rM" ((USItype) (ah)), \ 00249 "rM" ((USItype) (bh)), \ 00250 "%rM" ((USItype) (al)), \ 00251 "rM" ((USItype) (bl))) 00252 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00253 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ 00254 : "=r" ((USItype) (sh)), \ 00255 "=&r" ((USItype) (sl)) \ 00256 : "rM" ((USItype) (ah)), \ 00257 "rM" ((USItype) (bh)), \ 00258 "rM" ((USItype) (al)), \ 00259 "rM" ((USItype) (bl))) 00260 #if defined (_PA_RISC1_1) 00261 #define umul_ppmm(w1, w0, u, v) \ 00262 do { \ 00263 union \ 00264 { \ 00265 UDItype __f; \ 00266 struct {USItype __w1, __w0;} __w1w0; \ 00267 } __t; \ 00268 __asm__ ("xmpyu %1,%2,%0" \ 00269 : "=x" (__t.__f) \ 00270 : "x" ((USItype) (u)), \ 00271 "x" ((USItype) (v))); \ 00272 (w1) = __t.__w1w0.__w1; \ 00273 (w0) = __t.__w1w0.__w0; \ 00274 } while (0) 00275 #define UMUL_TIME 8 00276 #else 00277 #define UMUL_TIME 30 00278 #endif 00279 #define UDIV_TIME 40 00280 #define count_leading_zeros(count, x) \ 00281 do { \ 00282 USItype __tmp; \ 00283 __asm__ ( \ 00284 "ldi 1,%0\n" \ 00285 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ 00286 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\ 00287 " ldo 16(%0),%0 ; Yes. Perform add.\n" \ 00288 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ 00289 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\ 00290 " ldo 8(%0),%0 ; Yes. Perform add.\n" \ 00291 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ 00292 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\ 00293 " ldo 4(%0),%0 ; Yes. Perform add.\n" \ 00294 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ 00295 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\ 00296 " ldo 2(%0),%0 ; Yes. Perform add.\n" \ 00297 " extru %1,30,1,%1 ; Extract bit 1.\n" \ 00298 " sub %0,%1,%0 ; Subtract it.\n" \ 00299 : "=r" (count), "=r" (__tmp) : "1" (x)); \ 00300 } while (0) 00301 #endif 00302 00303 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32 00304 #define smul_ppmm(xh, xl, m0, m1) \ 00305 do { \ 00306 union {DItype __ll; \ 00307 struct {USItype __h, __l;} __i; \ 00308 } __x; \ 00309 __asm__ ("lr %N0,%1\n\tmr %0,%2" \ 00310 : "=&r" (__x.__ll) \ 00311 : "r" (m0), "r" (m1)); \ 00312 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \ 00313 } while (0) 00314 #define sdiv_qrnnd(q, r, n1, n0, d) \ 00315 do { \ 00316 union {DItype __ll; \ 00317 struct {USItype __h, __l;} __i; \ 00318 } __x; \ 00319 __x.__i.__h = n1; __x.__i.__l = n0; \ 00320 __asm__ ("dr %0,%2" \ 00321 : "=r" (__x.__ll) \ 00322 : "0" (__x.__ll), "r" (d)); \ 00323 (q) = __x.__i.__l; (r) = __x.__i.__h; \ 00324 } while (0) 00325 #endif 00326 00327 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 00328 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00329 __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \ 00330 : "=r" ((USItype) (sh)), \ 00331 "=&r" ((USItype) (sl)) \ 00332 : "%0" ((USItype) (ah)), \ 00333 "g" ((USItype) (bh)), \ 00334 "%1" ((USItype) (al)), \ 00335 "g" ((USItype) (bl))) 00336 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00337 __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \ 00338 : "=r" ((USItype) (sh)), \ 00339 "=&r" ((USItype) (sl)) \ 00340 : "0" ((USItype) (ah)), \ 00341 "g" ((USItype) (bh)), \ 00342 "1" ((USItype) (al)), \ 00343 "g" ((USItype) (bl))) 00344 #define umul_ppmm(w1, w0, u, v) \ 00345 __asm__ ("mul{l} %3" \ 00346 : "=a" ((USItype) (w0)), \ 00347 "=d" ((USItype) (w1)) \ 00348 : "%0" ((USItype) (u)), \ 00349 "rm" ((USItype) (v))) 00350 #define udiv_qrnnd(q, r, n1, n0, dv) \ 00351 __asm__ ("div{l} %4" \ 00352 : "=a" ((USItype) (q)), \ 00353 "=d" ((USItype) (r)) \ 00354 : "0" ((USItype) (n0)), \ 00355 "1" ((USItype) (n1)), \ 00356 "rm" ((USItype) (dv))) 00357 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x)) 00358 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x)) 00359 #define UMUL_TIME 40 00360 #define UDIV_TIME 40 00361 #endif /* 80x86 */ 00362 00363 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64 00364 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00365 __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \ 00366 : "=r" ((UDItype) (sh)), \ 00367 "=&r" ((UDItype) (sl)) \ 00368 : "%0" ((UDItype) (ah)), \ 00369 "rme" ((UDItype) (bh)), \ 00370 "%1" ((UDItype) (al)), \ 00371 "rme" ((UDItype) (bl))) 00372 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00373 __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \ 00374 : "=r" ((UDItype) (sh)), \ 00375 "=&r" ((UDItype) (sl)) \ 00376 : "0" ((UDItype) (ah)), \ 00377 "rme" ((UDItype) (bh)), \ 00378 "1" ((UDItype) (al)), \ 00379 "rme" ((UDItype) (bl))) 00380 #define umul_ppmm(w1, w0, u, v) \ 00381 __asm__ ("mul{q} %3" \ 00382 : "=a" ((UDItype) (w0)), \ 00383 "=d" ((UDItype) (w1)) \ 00384 : "%0" ((UDItype) (u)), \ 00385 "rm" ((UDItype) (v))) 00386 #define udiv_qrnnd(q, r, n1, n0, dv) \ 00387 __asm__ ("div{q} %4" \ 00388 : "=a" ((UDItype) (q)), \ 00389 "=d" ((UDItype) (r)) \ 00390 : "0" ((UDItype) (n0)), \ 00391 "1" ((UDItype) (n1)), \ 00392 "rm" ((UDItype) (dv))) 00393 #define count_leading_zeros(count, x) ((count) = __builtin_clzl (x)) 00394 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x)) 00395 #define UMUL_TIME 40 00396 #define UDIV_TIME 40 00397 #endif /* x86_64 */ 00398 00399 #if defined (__i960__) && W_TYPE_SIZE == 32 00400 #define umul_ppmm(w1, w0, u, v) \ 00401 ({union {UDItype __ll; \ 00402 struct {USItype __l, __h;} __i; \ 00403 } __xx; \ 00404 __asm__ ("emul %2,%1,%0" \ 00405 : "=d" (__xx.__ll) \ 00406 : "%dI" ((USItype) (u)), \ 00407 "dI" ((USItype) (v))); \ 00408 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 00409 #define __umulsidi3(u, v) \ 00410 ({UDItype __w; \ 00411 __asm__ ("emul %2,%1,%0" \ 00412 : "=d" (__w) \ 00413 : "%dI" ((USItype) (u)), \ 00414 "dI" ((USItype) (v))); \ 00415 __w; }) 00416 #endif /* __i960__ */ 00417 00418 #if defined (__M32R__) && W_TYPE_SIZE == 32 00419 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00420 /* The cmp clears the condition bit. */ \ 00421 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \ 00422 : "=r" ((USItype) (sh)), \ 00423 "=&r" ((USItype) (sl)) \ 00424 : "0" ((USItype) (ah)), \ 00425 "r" ((USItype) (bh)), \ 00426 "1" ((USItype) (al)), \ 00427 "r" ((USItype) (bl)) \ 00428 : "cbit") 00429 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00430 /* The cmp clears the condition bit. */ \ 00431 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \ 00432 : "=r" ((USItype) (sh)), \ 00433 "=&r" ((USItype) (sl)) \ 00434 : "0" ((USItype) (ah)), \ 00435 "r" ((USItype) (bh)), \ 00436 "1" ((USItype) (al)), \ 00437 "r" ((USItype) (bl)) \ 00438 : "cbit") 00439 #endif /* __M32R__ */ 00440 00441 #if defined (__mc68000__) && W_TYPE_SIZE == 32 00442 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00443 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ 00444 : "=d" ((USItype) (sh)), \ 00445 "=&d" ((USItype) (sl)) \ 00446 : "%0" ((USItype) (ah)), \ 00447 "d" ((USItype) (bh)), \ 00448 "%1" ((USItype) (al)), \ 00449 "g" ((USItype) (bl))) 00450 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00451 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ 00452 : "=d" ((USItype) (sh)), \ 00453 "=&d" ((USItype) (sl)) \ 00454 : "0" ((USItype) (ah)), \ 00455 "d" ((USItype) (bh)), \ 00456 "1" ((USItype) (al)), \ 00457 "g" ((USItype) (bl))) 00458 00459 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */ 00460 #if (defined (__mc68020__) && !defined (__mc68060__)) 00461 #define umul_ppmm(w1, w0, u, v) \ 00462 __asm__ ("mulu%.l %3,%1:%0" \ 00463 : "=d" ((USItype) (w0)), \ 00464 "=d" ((USItype) (w1)) \ 00465 : "%0" ((USItype) (u)), \ 00466 "dmi" ((USItype) (v))) 00467 #define UMUL_TIME 45 00468 #define udiv_qrnnd(q, r, n1, n0, d) \ 00469 __asm__ ("divu%.l %4,%1:%0" \ 00470 : "=d" ((USItype) (q)), \ 00471 "=d" ((USItype) (r)) \ 00472 : "0" ((USItype) (n0)), \ 00473 "1" ((USItype) (n1)), \ 00474 "dmi" ((USItype) (d))) 00475 #define UDIV_TIME 90 00476 #define sdiv_qrnnd(q, r, n1, n0, d) \ 00477 __asm__ ("divs%.l %4,%1:%0" \ 00478 : "=d" ((USItype) (q)), \ 00479 "=d" ((USItype) (r)) \ 00480 : "0" ((USItype) (n0)), \ 00481 "1" ((USItype) (n1)), \ 00482 "dmi" ((USItype) (d))) 00483 00484 #elif defined (__mcoldfire__) /* not mc68020 */ 00485 00486 #define umul_ppmm(xh, xl, a, b) \ 00487 __asm__ ("| Inlined umul_ppmm\n" \ 00488 " move%.l %2,%/d0\n" \ 00489 " move%.l %3,%/d1\n" \ 00490 " move%.l %/d0,%/d2\n" \ 00491 " swap %/d0\n" \ 00492 " move%.l %/d1,%/d3\n" \ 00493 " swap %/d1\n" \ 00494 " move%.w %/d2,%/d4\n" \ 00495 " mulu %/d3,%/d4\n" \ 00496 " mulu %/d1,%/d2\n" \ 00497 " mulu %/d0,%/d3\n" \ 00498 " mulu %/d0,%/d1\n" \ 00499 " move%.l %/d4,%/d0\n" \ 00500 " clr%.w %/d0\n" \ 00501 " swap %/d0\n" \ 00502 " add%.l %/d0,%/d2\n" \ 00503 " add%.l %/d3,%/d2\n" \ 00504 " jcc 1f\n" \ 00505 " add%.l %#65536,%/d1\n" \ 00506 "1: swap %/d2\n" \ 00507 " moveq %#0,%/d0\n" \ 00508 " move%.w %/d2,%/d0\n" \ 00509 " move%.w %/d4,%/d2\n" \ 00510 " move%.l %/d2,%1\n" \ 00511 " add%.l %/d1,%/d0\n" \ 00512 " move%.l %/d0,%0" \ 00513 : "=g" ((USItype) (xh)), \ 00514 "=g" ((USItype) (xl)) \ 00515 : "g" ((USItype) (a)), \ 00516 "g" ((USItype) (b)) \ 00517 : "d0", "d1", "d2", "d3", "d4") 00518 #define UMUL_TIME 100 00519 #define UDIV_TIME 400 00520 #else /* not ColdFire */ 00521 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ 00522 #define umul_ppmm(xh, xl, a, b) \ 00523 __asm__ ("| Inlined umul_ppmm\n" \ 00524 " move%.l %2,%/d0\n" \ 00525 " move%.l %3,%/d1\n" \ 00526 " move%.l %/d0,%/d2\n" \ 00527 " swap %/d0\n" \ 00528 " move%.l %/d1,%/d3\n" \ 00529 " swap %/d1\n" \ 00530 " move%.w %/d2,%/d4\n" \ 00531 " mulu %/d3,%/d4\n" \ 00532 " mulu %/d1,%/d2\n" \ 00533 " mulu %/d0,%/d3\n" \ 00534 " mulu %/d0,%/d1\n" \ 00535 " move%.l %/d4,%/d0\n" \ 00536 " eor%.w %/d0,%/d0\n" \ 00537 " swap %/d0\n" \ 00538 " add%.l %/d0,%/d2\n" \ 00539 " add%.l %/d3,%/d2\n" \ 00540 " jcc 1f\n" \ 00541 " add%.l %#65536,%/d1\n" \ 00542 "1: swap %/d2\n" \ 00543 " moveq %#0,%/d0\n" \ 00544 " move%.w %/d2,%/d0\n" \ 00545 " move%.w %/d4,%/d2\n" \ 00546 " move%.l %/d2,%1\n" \ 00547 " add%.l %/d1,%/d0\n" \ 00548 " move%.l %/d0,%0" \ 00549 : "=g" ((USItype) (xh)), \ 00550 "=g" ((USItype) (xl)) \ 00551 : "g" ((USItype) (a)), \ 00552 "g" ((USItype) (b)) \ 00553 : "d0", "d1", "d2", "d3", "d4") 00554 #define UMUL_TIME 100 00555 #define UDIV_TIME 400 00556 00557 #endif /* not mc68020 */ 00558 00559 /* The '020, '030, '040 and '060 have bitfield insns. 00560 cpu32 disguises as a 68020, but lacks them. */ 00561 #if defined (__mc68020__) && !defined (__mcpu32__) 00562 #define count_leading_zeros(count, x) \ 00563 __asm__ ("bfffo %1{%b2:%b2},%0" \ 00564 : "=d" ((USItype) (count)) \ 00565 : "od" ((USItype) (x)), "n" (0)) 00566 /* Some ColdFire architectures have a ff1 instruction supported via 00567 __builtin_clz. */ 00568 #elif defined (__mcfisaaplus__) || defined (__mcfisac__) 00569 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x)) 00570 #define COUNT_LEADING_ZEROS_0 32 00571 #endif 00572 #endif /* mc68000 */ 00573 00574 #if defined (__m88000__) && W_TYPE_SIZE == 32 00575 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00576 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ 00577 : "=r" ((USItype) (sh)), \ 00578 "=&r" ((USItype) (sl)) \ 00579 : "%rJ" ((USItype) (ah)), \ 00580 "rJ" ((USItype) (bh)), \ 00581 "%rJ" ((USItype) (al)), \ 00582 "rJ" ((USItype) (bl))) 00583 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00584 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ 00585 : "=r" ((USItype) (sh)), \ 00586 "=&r" ((USItype) (sl)) \ 00587 : "rJ" ((USItype) (ah)), \ 00588 "rJ" ((USItype) (bh)), \ 00589 "rJ" ((USItype) (al)), \ 00590 "rJ" ((USItype) (bl))) 00591 #define count_leading_zeros(count, x) \ 00592 do { \ 00593 USItype __cbtmp; \ 00594 __asm__ ("ff1 %0,%1" \ 00595 : "=r" (__cbtmp) \ 00596 : "r" ((USItype) (x))); \ 00597 (count) = __cbtmp ^ 31; \ 00598 } while (0) 00599 #define COUNT_LEADING_ZEROS_0 63 /* sic */ 00600 #if defined (__mc88110__) 00601 #define umul_ppmm(wh, wl, u, v) \ 00602 do { \ 00603 union {UDItype __ll; \ 00604 struct {USItype __h, __l;} __i; \ 00605 } __xx; \ 00606 __asm__ ("mulu.d %0,%1,%2" \ 00607 : "=r" (__xx.__ll) \ 00608 : "r" ((USItype) (u)), \ 00609 "r" ((USItype) (v))); \ 00610 (wh) = __xx.__i.__h; \ 00611 (wl) = __xx.__i.__l; \ 00612 } while (0) 00613 #define udiv_qrnnd(q, r, n1, n0, d) \ 00614 ({union {UDItype __ll; \ 00615 struct {USItype __h, __l;} __i; \ 00616 } __xx; \ 00617 USItype __q; \ 00618 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 00619 __asm__ ("divu.d %0,%1,%2" \ 00620 : "=r" (__q) \ 00621 : "r" (__xx.__ll), \ 00622 "r" ((USItype) (d))); \ 00623 (r) = (n0) - __q * (d); (q) = __q; }) 00624 #define UMUL_TIME 5 00625 #define UDIV_TIME 25 00626 #else 00627 #define UMUL_TIME 17 00628 #define UDIV_TIME 150 00629 #endif /* __mc88110__ */ 00630 #endif /* __m88000__ */ 00631 00632 #if defined (__mips__) && W_TYPE_SIZE == 32 00633 #define umul_ppmm(w1, w0, u, v) \ 00634 do { \ 00635 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \ 00636 (w1) = (USItype) (__x >> 32); \ 00637 (w0) = (USItype) (__x); \ 00638 } while (0) 00639 #define UMUL_TIME 10 00640 #define UDIV_TIME 100 00641 00642 #if (__mips == 32 || __mips == 64) && ! __mips16 00643 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X)) 00644 #define COUNT_LEADING_ZEROS_0 32 00645 #endif 00646 #endif /* __mips__ */ 00647 00648 #if defined (__ns32000__) && W_TYPE_SIZE == 32 00649 #define umul_ppmm(w1, w0, u, v) \ 00650 ({union {UDItype __ll; \ 00651 struct {USItype __l, __h;} __i; \ 00652 } __xx; \ 00653 __asm__ ("meid %2,%0" \ 00654 : "=g" (__xx.__ll) \ 00655 : "%0" ((USItype) (u)), \ 00656 "g" ((USItype) (v))); \ 00657 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 00658 #define __umulsidi3(u, v) \ 00659 ({UDItype __w; \ 00660 __asm__ ("meid %2,%0" \ 00661 : "=g" (__w) \ 00662 : "%0" ((USItype) (u)), \ 00663 "g" ((USItype) (v))); \ 00664 __w; }) 00665 #define udiv_qrnnd(q, r, n1, n0, d) \ 00666 ({union {UDItype __ll; \ 00667 struct {USItype __l, __h;} __i; \ 00668 } __xx; \ 00669 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 00670 __asm__ ("deid %2,%0" \ 00671 : "=g" (__xx.__ll) \ 00672 : "0" (__xx.__ll), \ 00673 "g" ((USItype) (d))); \ 00674 (r) = __xx.__i.__l; (q) = __xx.__i.__h; }) 00675 #define count_trailing_zeros(count,x) \ 00676 do { \ 00677 __asm__ ("ffsd %2,%0" \ 00678 : "=r" ((USItype) (count)) \ 00679 : "0" ((USItype) 0), \ 00680 "r" ((USItype) (x))); \ 00681 } while (0) 00682 #endif /* __ns32000__ */ 00683 00684 /* FIXME: We should test _IBMR2 here when we add assembly support for the 00685 system vendor compilers. 00686 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good 00687 enough, since that hits ARM and m68k too. */ 00688 #if (defined (_ARCH_PPC) /* AIX */ \ 00689 || defined (_ARCH_PWR) /* AIX */ \ 00690 || defined (_ARCH_COM) /* AIX */ \ 00691 || defined (__powerpc__) /* gcc */ \ 00692 || defined (__POWERPC__) /* BEOS */ \ 00693 || defined (__ppc__) /* Darwin */ \ 00694 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ 00695 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ 00696 && CPU_FAMILY == PPC) \ 00697 ) && W_TYPE_SIZE == 32 00698 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00699 do { \ 00700 if (__builtin_constant_p (bh) && (bh) == 0) \ 00701 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 00702 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 00703 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 00704 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 00705 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 00706 else \ 00707 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 00708 : "=r" (sh), "=&r" (sl) \ 00709 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 00710 } while (0) 00711 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00712 do { \ 00713 if (__builtin_constant_p (ah) && (ah) == 0) \ 00714 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 00715 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 00716 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ 00717 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 00718 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 00719 else if (__builtin_constant_p (bh) && (bh) == 0) \ 00720 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 00721 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 00722 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 00723 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 00724 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 00725 else \ 00726 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 00727 : "=r" (sh), "=&r" (sl) \ 00728 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 00729 } while (0) 00730 #define count_leading_zeros(count, x) \ 00731 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) 00732 #define COUNT_LEADING_ZEROS_0 32 00733 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ 00734 || defined (__ppc__) \ 00735 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ 00736 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ 00737 && CPU_FAMILY == PPC) 00738 #define umul_ppmm(ph, pl, m0, m1) \ 00739 do { \ 00740 USItype __m0 = (m0), __m1 = (m1); \ 00741 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 00742 (pl) = __m0 * __m1; \ 00743 } while (0) 00744 #define UMUL_TIME 15 00745 #define smul_ppmm(ph, pl, m0, m1) \ 00746 do { \ 00747 SItype __m0 = (m0), __m1 = (m1); \ 00748 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 00749 (pl) = __m0 * __m1; \ 00750 } while (0) 00751 #define SMUL_TIME 14 00752 #define UDIV_TIME 120 00753 #elif defined (_ARCH_PWR) 00754 #define UMUL_TIME 8 00755 #define smul_ppmm(xh, xl, m0, m1) \ 00756 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1)) 00757 #define SMUL_TIME 4 00758 #define sdiv_qrnnd(q, r, nh, nl, d) \ 00759 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d)) 00760 #define UDIV_TIME 100 00761 #endif 00762 #endif /* 32-bit POWER architecture variants. */ 00763 00764 /* We should test _IBMR2 here when we add assembly support for the system 00765 vendor compilers. */ 00766 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64 00767 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00768 do { \ 00769 if (__builtin_constant_p (bh) && (bh) == 0) \ 00770 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 00771 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 00772 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 00773 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 00774 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 00775 else \ 00776 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 00777 : "=r" (sh), "=&r" (sl) \ 00778 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 00779 } while (0) 00780 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00781 do { \ 00782 if (__builtin_constant_p (ah) && (ah) == 0) \ 00783 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 00784 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 00785 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ 00786 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 00787 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 00788 else if (__builtin_constant_p (bh) && (bh) == 0) \ 00789 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 00790 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 00791 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 00792 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 00793 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 00794 else \ 00795 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 00796 : "=r" (sh), "=&r" (sl) \ 00797 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 00798 } while (0) 00799 #define count_leading_zeros(count, x) \ 00800 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x)) 00801 #define COUNT_LEADING_ZEROS_0 64 00802 #define umul_ppmm(ph, pl, m0, m1) \ 00803 do { \ 00804 UDItype __m0 = (m0), __m1 = (m1); \ 00805 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 00806 (pl) = __m0 * __m1; \ 00807 } while (0) 00808 #define UMUL_TIME 15 00809 #define smul_ppmm(ph, pl, m0, m1) \ 00810 do { \ 00811 DItype __m0 = (m0), __m1 = (m1); \ 00812 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 00813 (pl) = __m0 * __m1; \ 00814 } while (0) 00815 #define SMUL_TIME 14 /* ??? */ 00816 #define UDIV_TIME 120 /* ??? */ 00817 #endif /* 64-bit PowerPC. */ 00818 00819 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 00820 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00821 __asm__ ("a %1,%5\n\tae %0,%3" \ 00822 : "=r" ((USItype) (sh)), \ 00823 "=&r" ((USItype) (sl)) \ 00824 : "%0" ((USItype) (ah)), \ 00825 "r" ((USItype) (bh)), \ 00826 "%1" ((USItype) (al)), \ 00827 "r" ((USItype) (bl))) 00828 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00829 __asm__ ("s %1,%5\n\tse %0,%3" \ 00830 : "=r" ((USItype) (sh)), \ 00831 "=&r" ((USItype) (sl)) \ 00832 : "0" ((USItype) (ah)), \ 00833 "r" ((USItype) (bh)), \ 00834 "1" ((USItype) (al)), \ 00835 "r" ((USItype) (bl))) 00836 #define umul_ppmm(ph, pl, m0, m1) \ 00837 do { \ 00838 USItype __m0 = (m0), __m1 = (m1); \ 00839 __asm__ ( \ 00840 "s r2,r2\n" \ 00841 " mts r10,%2\n" \ 00842 " m r2,%3\n" \ 00843 " m r2,%3\n" \ 00844 " m r2,%3\n" \ 00845 " m r2,%3\n" \ 00846 " m r2,%3\n" \ 00847 " m r2,%3\n" \ 00848 " m r2,%3\n" \ 00849 " m r2,%3\n" \ 00850 " m r2,%3\n" \ 00851 " m r2,%3\n" \ 00852 " m r2,%3\n" \ 00853 " m r2,%3\n" \ 00854 " m r2,%3\n" \ 00855 " m r2,%3\n" \ 00856 " m r2,%3\n" \ 00857 " m r2,%3\n" \ 00858 " cas %0,r2,r0\n" \ 00859 " mfs r10,%1" \ 00860 : "=r" ((USItype) (ph)), \ 00861 "=r" ((USItype) (pl)) \ 00862 : "%r" (__m0), \ 00863 "r" (__m1) \ 00864 : "r2"); \ 00865 (ph) += ((((SItype) __m0 >> 31) & __m1) \ 00866 + (((SItype) __m1 >> 31) & __m0)); \ 00867 } while (0) 00868 #define UMUL_TIME 20 00869 #define UDIV_TIME 200 00870 #define count_leading_zeros(count, x) \ 00871 do { \ 00872 if ((x) >= 0x10000) \ 00873 __asm__ ("clz %0,%1" \ 00874 : "=r" ((USItype) (count)) \ 00875 : "r" ((USItype) (x) >> 16)); \ 00876 else \ 00877 { \ 00878 __asm__ ("clz %0,%1" \ 00879 : "=r" ((USItype) (count)) \ 00880 : "r" ((USItype) (x))); \ 00881 (count) += 16; \ 00882 } \ 00883 } while (0) 00884 #endif 00885 00886 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32 00887 #ifndef __sh1__ 00888 #define umul_ppmm(w1, w0, u, v) \ 00889 __asm__ ( \ 00890 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \ 00891 : "=r<" ((USItype)(w1)), \ 00892 "=r<" ((USItype)(w0)) \ 00893 : "r" ((USItype)(u)), \ 00894 "r" ((USItype)(v)) \ 00895 : "macl", "mach") 00896 #define UMUL_TIME 5 00897 #endif 00898 00899 /* This is the same algorithm as __udiv_qrnnd_c. */ 00900 #define UDIV_NEEDS_NORMALIZATION 1 00901 00902 #define udiv_qrnnd(q, r, n1, n0, d) \ 00903 do { \ 00904 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \ 00905 __attribute__ ((visibility ("hidden"))); \ 00906 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \ 00907 __asm__ ( \ 00908 "mov%M4 %4,r5\n" \ 00909 " swap.w %3,r4\n" \ 00910 " swap.w r5,r6\n" \ 00911 " jsr @%5\n" \ 00912 " shll16 r6\n" \ 00913 " swap.w r4,r4\n" \ 00914 " jsr @%5\n" \ 00915 " swap.w r1,%0\n" \ 00916 " or r1,%0" \ 00917 : "=r" (q), "=&z" (r) \ 00918 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \ 00919 : "r1", "r2", "r4", "r5", "r6", "pr"); \ 00920 } while (0) 00921 00922 #define UDIV_TIME 80 00923 00924 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00925 __asm__ ("clrt;subc %5,%1; subc %4,%0" \ 00926 : "=r" (sh), "=r" (sl) \ 00927 : "0" (ah), "1" (al), "r" (bh), "r" (bl)) 00928 00929 #endif /* __sh__ */ 00930 00931 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32 00932 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v) 00933 #define count_leading_zeros(count, x) \ 00934 do \ 00935 { \ 00936 UDItype x_ = (USItype)(x); \ 00937 SItype c_; \ 00938 \ 00939 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \ 00940 (count) = c_ - 31; \ 00941 } \ 00942 while (0) 00943 #define COUNT_LEADING_ZEROS_0 32 00944 #endif 00945 00946 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \ 00947 && W_TYPE_SIZE == 32 00948 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 00949 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ 00950 : "=r" ((USItype) (sh)), \ 00951 "=&r" ((USItype) (sl)) \ 00952 : "%rJ" ((USItype) (ah)), \ 00953 "rI" ((USItype) (bh)), \ 00954 "%rJ" ((USItype) (al)), \ 00955 "rI" ((USItype) (bl)) \ 00956 __CLOBBER_CC) 00957 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 00958 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ 00959 : "=r" ((USItype) (sh)), \ 00960 "=&r" ((USItype) (sl)) \ 00961 : "rJ" ((USItype) (ah)), \ 00962 "rI" ((USItype) (bh)), \ 00963 "rJ" ((USItype) (al)), \ 00964 "rI" ((USItype) (bl)) \ 00965 __CLOBBER_CC) 00966 #if defined (__sparc_v8__) 00967 #define umul_ppmm(w1, w0, u, v) \ 00968 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 00969 : "=r" ((USItype) (w1)), \ 00970 "=r" ((USItype) (w0)) \ 00971 : "r" ((USItype) (u)), \ 00972 "r" ((USItype) (v))) 00973 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 00974 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ 00975 : "=&r" ((USItype) (__q)), \ 00976 "=&r" ((USItype) (__r)) \ 00977 : "r" ((USItype) (__n1)), \ 00978 "r" ((USItype) (__n0)), \ 00979 "r" ((USItype) (__d))) 00980 #else 00981 #if defined (__sparclite__) 00982 /* This has hardware multiply but not divide. It also has two additional 00983 instructions scan (ffs from high bit) and divscc. */ 00984 #define umul_ppmm(w1, w0, u, v) \ 00985 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 00986 : "=r" ((USItype) (w1)), \ 00987 "=r" ((USItype) (w0)) \ 00988 : "r" ((USItype) (u)), \ 00989 "r" ((USItype) (v))) 00990 #define udiv_qrnnd(q, r, n1, n0, d) \ 00991 __asm__ ("! Inlined udiv_qrnnd\n" \ 00992 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ 00993 " tst %%g0\n" \ 00994 " divscc %3,%4,%%g1\n" \ 00995 " divscc %%g1,%4,%%g1\n" \ 00996 " divscc %%g1,%4,%%g1\n" \ 00997 " divscc %%g1,%4,%%g1\n" \ 00998 " divscc %%g1,%4,%%g1\n" \ 00999 " divscc %%g1,%4,%%g1\n" \ 01000 " divscc %%g1,%4,%%g1\n" \ 01001 " divscc %%g1,%4,%%g1\n" \ 01002 " divscc %%g1,%4,%%g1\n" \ 01003 " divscc %%g1,%4,%%g1\n" \ 01004 " divscc %%g1,%4,%%g1\n" \ 01005 " divscc %%g1,%4,%%g1\n" \ 01006 " divscc %%g1,%4,%%g1\n" \ 01007 " divscc %%g1,%4,%%g1\n" \ 01008 " divscc %%g1,%4,%%g1\n" \ 01009 " divscc %%g1,%4,%%g1\n" \ 01010 " divscc %%g1,%4,%%g1\n" \ 01011 " divscc %%g1,%4,%%g1\n" \ 01012 " divscc %%g1,%4,%%g1\n" \ 01013 " divscc %%g1,%4,%%g1\n" \ 01014 " divscc %%g1,%4,%%g1\n" \ 01015 " divscc %%g1,%4,%%g1\n" \ 01016 " divscc %%g1,%4,%%g1\n" \ 01017 " divscc %%g1,%4,%%g1\n" \ 01018 " divscc %%g1,%4,%%g1\n" \ 01019 " divscc %%g1,%4,%%g1\n" \ 01020 " divscc %%g1,%4,%%g1\n" \ 01021 " divscc %%g1,%4,%%g1\n" \ 01022 " divscc %%g1,%4,%%g1\n" \ 01023 " divscc %%g1,%4,%%g1\n" \ 01024 " divscc %%g1,%4,%%g1\n" \ 01025 " divscc %%g1,%4,%0\n" \ 01026 " rd %%y,%1\n" \ 01027 " bl,a 1f\n" \ 01028 " add %1,%4,%1\n" \ 01029 "1: ! End of inline udiv_qrnnd" \ 01030 : "=r" ((USItype) (q)), \ 01031 "=r" ((USItype) (r)) \ 01032 : "r" ((USItype) (n1)), \ 01033 "r" ((USItype) (n0)), \ 01034 "rI" ((USItype) (d)) \ 01035 : "g1" __AND_CLOBBER_CC) 01036 #define UDIV_TIME 37 01037 #define count_leading_zeros(count, x) \ 01038 do { \ 01039 __asm__ ("scan %1,1,%0" \ 01040 : "=r" ((USItype) (count)) \ 01041 : "r" ((USItype) (x))); \ 01042 } while (0) 01043 /* Early sparclites return 63 for an argument of 0, but they warn that future 01044 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 01045 undefined. */ 01046 #else 01047 /* SPARC without integer multiplication and divide instructions. 01048 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ 01049 #define umul_ppmm(w1, w0, u, v) \ 01050 __asm__ ("! Inlined umul_ppmm\n" \ 01051 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\ 01052 " sra %3,31,%%o5 ! Don't move this insn\n" \ 01053 " and %2,%%o5,%%o5 ! Don't move this insn\n" \ 01054 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \ 01055 " mulscc %%g1,%3,%%g1\n" \ 01056 " mulscc %%g1,%3,%%g1\n" \ 01057 " mulscc %%g1,%3,%%g1\n" \ 01058 " mulscc %%g1,%3,%%g1\n" \ 01059 " mulscc %%g1,%3,%%g1\n" \ 01060 " mulscc %%g1,%3,%%g1\n" \ 01061 " mulscc %%g1,%3,%%g1\n" \ 01062 " mulscc %%g1,%3,%%g1\n" \ 01063 " mulscc %%g1,%3,%%g1\n" \ 01064 " mulscc %%g1,%3,%%g1\n" \ 01065 " mulscc %%g1,%3,%%g1\n" \ 01066 " mulscc %%g1,%3,%%g1\n" \ 01067 " mulscc %%g1,%3,%%g1\n" \ 01068 " mulscc %%g1,%3,%%g1\n" \ 01069 " mulscc %%g1,%3,%%g1\n" \ 01070 " mulscc %%g1,%3,%%g1\n" \ 01071 " mulscc %%g1,%3,%%g1\n" \ 01072 " mulscc %%g1,%3,%%g1\n" \ 01073 " mulscc %%g1,%3,%%g1\n" \ 01074 " mulscc %%g1,%3,%%g1\n" \ 01075 " mulscc %%g1,%3,%%g1\n" \ 01076 " mulscc %%g1,%3,%%g1\n" \ 01077 " mulscc %%g1,%3,%%g1\n" \ 01078 " mulscc %%g1,%3,%%g1\n" \ 01079 " mulscc %%g1,%3,%%g1\n" \ 01080 " mulscc %%g1,%3,%%g1\n" \ 01081 " mulscc %%g1,%3,%%g1\n" \ 01082 " mulscc %%g1,%3,%%g1\n" \ 01083 " mulscc %%g1,%3,%%g1\n" \ 01084 " mulscc %%g1,%3,%%g1\n" \ 01085 " mulscc %%g1,%3,%%g1\n" \ 01086 " mulscc %%g1,%3,%%g1\n" \ 01087 " mulscc %%g1,0,%%g1\n" \ 01088 " add %%g1,%%o5,%0\n" \ 01089 " rd %%y,%1" \ 01090 : "=r" ((USItype) (w1)), \ 01091 "=r" ((USItype) (w0)) \ 01092 : "%rI" ((USItype) (u)), \ 01093 "r" ((USItype) (v)) \ 01094 : "g1", "o5" __AND_CLOBBER_CC) 01095 #define UMUL_TIME 39 /* 39 instructions */ 01096 /* It's quite necessary to add this much assembler for the sparc. 01097 The default udiv_qrnnd (in C) is more than 10 times slower! */ 01098 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 01099 __asm__ ("! Inlined udiv_qrnnd\n" \ 01100 " mov 32,%%g1\n" \ 01101 " subcc %1,%2,%%g0\n" \ 01102 "1: bcs 5f\n" \ 01103 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 01104 " sub %1,%2,%1 ! this kills msb of n\n" \ 01105 " addx %1,%1,%1 ! so this can't give carry\n" \ 01106 " subcc %%g1,1,%%g1\n" \ 01107 "2: bne 1b\n" \ 01108 " subcc %1,%2,%%g0\n" \ 01109 " bcs 3f\n" \ 01110 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 01111 " b 3f\n" \ 01112 " sub %1,%2,%1 ! this kills msb of n\n" \ 01113 "4: sub %1,%2,%1\n" \ 01114 "5: addxcc %1,%1,%1\n" \ 01115 " bcc 2b\n" \ 01116 " subcc %%g1,1,%%g1\n" \ 01117 "! Got carry from n. Subtract next step to cancel this carry.\n" \ 01118 " bne 4b\n" \ 01119 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \ 01120 " sub %1,%2,%1\n" \ 01121 "3: xnor %0,0,%0\n" \ 01122 " ! End of inline udiv_qrnnd" \ 01123 : "=&r" ((USItype) (__q)), \ 01124 "=&r" ((USItype) (__r)) \ 01125 : "r" ((USItype) (__d)), \ 01126 "1" ((USItype) (__n1)), \ 01127 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) 01128 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ 01129 #endif /* __sparclite__ */ 01130 #endif /* __sparc_v8__ */ 01131 #endif /* sparc32 */ 01132 01133 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ 01134 && W_TYPE_SIZE == 64 01135 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 01136 __asm__ ("addcc %r4,%5,%1\n\t" \ 01137 "add %r2,%3,%0\n\t" \ 01138 "bcs,a,pn %%xcc, 1f\n\t" \ 01139 "add %0, 1, %0\n" \ 01140 "1:" \ 01141 : "=r" ((UDItype)(sh)), \ 01142 "=&r" ((UDItype)(sl)) \ 01143 : "%rJ" ((UDItype)(ah)), \ 01144 "rI" ((UDItype)(bh)), \ 01145 "%rJ" ((UDItype)(al)), \ 01146 "rI" ((UDItype)(bl)) \ 01147 __CLOBBER_CC) 01148 01149 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 01150 __asm__ ("subcc %r4,%5,%1\n\t" \ 01151 "sub %r2,%3,%0\n\t" \ 01152 "bcs,a,pn %%xcc, 1f\n\t" \ 01153 "sub %0, 1, %0\n\t" \ 01154 "1:" \ 01155 : "=r" ((UDItype)(sh)), \ 01156 "=&r" ((UDItype)(sl)) \ 01157 : "rJ" ((UDItype)(ah)), \ 01158 "rI" ((UDItype)(bh)), \ 01159 "rJ" ((UDItype)(al)), \ 01160 "rI" ((UDItype)(bl)) \ 01161 __CLOBBER_CC) 01162 01163 #define umul_ppmm(wh, wl, u, v) \ 01164 do { \ 01165 UDItype tmp1, tmp2, tmp3, tmp4; \ 01166 __asm__ __volatile__ ( \ 01167 "srl %7,0,%3\n\t" \ 01168 "mulx %3,%6,%1\n\t" \ 01169 "srlx %6,32,%2\n\t" \ 01170 "mulx %2,%3,%4\n\t" \ 01171 "sllx %4,32,%5\n\t" \ 01172 "srl %6,0,%3\n\t" \ 01173 "sub %1,%5,%5\n\t" \ 01174 "srlx %5,32,%5\n\t" \ 01175 "addcc %4,%5,%4\n\t" \ 01176 "srlx %7,32,%5\n\t" \ 01177 "mulx %3,%5,%3\n\t" \ 01178 "mulx %2,%5,%5\n\t" \ 01179 "sethi %%hi(0x80000000),%2\n\t" \ 01180 "addcc %4,%3,%4\n\t" \ 01181 "srlx %4,32,%4\n\t" \ 01182 "add %2,%2,%2\n\t" \ 01183 "movcc %%xcc,%%g0,%2\n\t" \ 01184 "addcc %5,%4,%5\n\t" \ 01185 "sllx %3,32,%3\n\t" \ 01186 "add %1,%3,%1\n\t" \ 01187 "add %5,%2,%0" \ 01188 : "=r" ((UDItype)(wh)), \ 01189 "=&r" ((UDItype)(wl)), \ 01190 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ 01191 : "r" ((UDItype)(u)), \ 01192 "r" ((UDItype)(v)) \ 01193 __CLOBBER_CC); \ 01194 } while (0) 01195 #define UMUL_TIME 96 01196 #define UDIV_TIME 230 01197 #endif /* sparc64 */ 01198 01199 #if defined (__vax__) && W_TYPE_SIZE == 32 01200 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 01201 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ 01202 : "=g" ((USItype) (sh)), \ 01203 "=&g" ((USItype) (sl)) \ 01204 : "%0" ((USItype) (ah)), \ 01205 "g" ((USItype) (bh)), \ 01206 "%1" ((USItype) (al)), \ 01207 "g" ((USItype) (bl))) 01208 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 01209 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ 01210 : "=g" ((USItype) (sh)), \ 01211 "=&g" ((USItype) (sl)) \ 01212 : "0" ((USItype) (ah)), \ 01213 "g" ((USItype) (bh)), \ 01214 "1" ((USItype) (al)), \ 01215 "g" ((USItype) (bl))) 01216 #define umul_ppmm(xh, xl, m0, m1) \ 01217 do { \ 01218 union { \ 01219 UDItype __ll; \ 01220 struct {USItype __l, __h;} __i; \ 01221 } __xx; \ 01222 USItype __m0 = (m0), __m1 = (m1); \ 01223 __asm__ ("emul %1,%2,$0,%0" \ 01224 : "=r" (__xx.__ll) \ 01225 : "g" (__m0), \ 01226 "g" (__m1)); \ 01227 (xh) = __xx.__i.__h; \ 01228 (xl) = __xx.__i.__l; \ 01229 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 01230 + (((SItype) __m1 >> 31) & __m0)); \ 01231 } while (0) 01232 #define sdiv_qrnnd(q, r, n1, n0, d) \ 01233 do { \ 01234 union {DItype __ll; \ 01235 struct {SItype __l, __h;} __i; \ 01236 } __xx; \ 01237 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 01238 __asm__ ("ediv %3,%2,%0,%1" \ 01239 : "=g" (q), "=g" (r) \ 01240 : "g" (__xx.__ll), "g" (d)); \ 01241 } while (0) 01242 #endif /* __vax__ */ 01243 01244 #if defined (__xtensa__) && W_TYPE_SIZE == 32 01245 /* This code is not Xtensa-configuration-specific, so rely on the compiler 01246 to expand builtin functions depending on what configuration features 01247 are available. This avoids library calls when the operation can be 01248 performed in-line. */ 01249 #define umul_ppmm(w1, w0, u, v) \ 01250 do { \ 01251 DWunion __w; \ 01252 __w.ll = __builtin_umulsidi3 (u, v); \ 01253 w1 = __w.s.high; \ 01254 w0 = __w.s.low; \ 01255 } while (0) 01256 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v) 01257 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X)) 01258 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X)) 01259 #endif /* __xtensa__ */ 01260 01261 #if defined (__z8000__) && W_TYPE_SIZE == 16 01262 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 01263 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ 01264 : "=r" ((unsigned int)(sh)), \ 01265 "=&r" ((unsigned int)(sl)) \ 01266 : "%0" ((unsigned int)(ah)), \ 01267 "r" ((unsigned int)(bh)), \ 01268 "%1" ((unsigned int)(al)), \ 01269 "rQR" ((unsigned int)(bl))) 01270 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 01271 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ 01272 : "=r" ((unsigned int)(sh)), \ 01273 "=&r" ((unsigned int)(sl)) \ 01274 : "0" ((unsigned int)(ah)), \ 01275 "r" ((unsigned int)(bh)), \ 01276 "1" ((unsigned int)(al)), \ 01277 "rQR" ((unsigned int)(bl))) 01278 #define umul_ppmm(xh, xl, m0, m1) \ 01279 do { \ 01280 union {long int __ll; \ 01281 struct {unsigned int __h, __l;} __i; \ 01282 } __xx; \ 01283 unsigned int __m0 = (m0), __m1 = (m1); \ 01284 __asm__ ("mult %S0,%H3" \ 01285 : "=r" (__xx.__i.__h), \ 01286 "=r" (__xx.__i.__l) \ 01287 : "%1" (__m0), \ 01288 "rQR" (__m1)); \ 01289 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 01290 (xh) += ((((signed int) __m0 >> 15) & __m1) \ 01291 + (((signed int) __m1 >> 15) & __m0)); \ 01292 } while (0) 01293 #endif /* __z8000__ */ 01294 01295 #endif /* __GNUC__ */ 01296 01297 /* If this machine has no inline assembler, use C macros. */ 01298 01299 #if !defined (add_ssaaaa) 01300 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 01301 do { \ 01302 UWtype __x; \ 01303 __x = (al) + (bl); \ 01304 (sh) = (ah) + (bh) + (__x < (al)); \ 01305 (sl) = __x; \ 01306 } while (0) 01307 #endif 01308 01309 #if !defined (sub_ddmmss) 01310 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 01311 do { \ 01312 UWtype __x; \ 01313 __x = (al) - (bl); \ 01314 (sh) = (ah) - (bh) - (__x > (al)); \ 01315 (sl) = __x; \ 01316 } while (0) 01317 #endif 01318 01319 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of 01320 smul_ppmm. */ 01321 #if !defined (umul_ppmm) && defined (smul_ppmm) 01322 #define umul_ppmm(w1, w0, u, v) \ 01323 do { \ 01324 UWtype __w1; \ 01325 UWtype __xm0 = (u), __xm1 = (v); \ 01326 smul_ppmm (__w1, w0, __xm0, __xm1); \ 01327 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \ 01328 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \ 01329 } while (0) 01330 #endif 01331 01332 /* If we still don't have umul_ppmm, define it using plain C. */ 01333 #if !defined (umul_ppmm) 01334 #define umul_ppmm(w1, w0, u, v) \ 01335 do { \ 01336 UWtype __x0, __x1, __x2, __x3; \ 01337 UHWtype __ul, __vl, __uh, __vh; \ 01338 \ 01339 __ul = __ll_lowpart (u); \ 01340 __uh = __ll_highpart (u); \ 01341 __vl = __ll_lowpart (v); \ 01342 __vh = __ll_highpart (v); \ 01343 \ 01344 __x0 = (UWtype) __ul * __vl; \ 01345 __x1 = (UWtype) __ul * __vh; \ 01346 __x2 = (UWtype) __uh * __vl; \ 01347 __x3 = (UWtype) __uh * __vh; \ 01348 \ 01349 __x1 += __ll_highpart (__x0);/* this can't give carry */ \ 01350 __x1 += __x2; /* but this indeed can */ \ 01351 if (__x1 < __x2) /* did we get it? */ \ 01352 __x3 += __ll_B; /* yes, add it in the proper pos. */ \ 01353 \ 01354 (w1) = __x3 + __ll_highpart (__x1); \ 01355 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ 01356 } while (0) 01357 #endif 01358 01359 #if !defined (__umulsidi3) 01360 #define __umulsidi3(u, v) \ 01361 ({DWunion __w; \ 01362 umul_ppmm (__w.s.high, __w.s.low, u, v); \ 01363 __w.ll; }) 01364 #endif 01365 01366 /* Define this unconditionally, so it can be used for debugging. */ 01367 #define __udiv_qrnnd_c(q, r, n1, n0, d) \ 01368 do { \ 01369 UWtype __d1, __d0, __q1, __q0; \ 01370 UWtype __r1, __r0, __m; \ 01371 __d1 = __ll_highpart (d); \ 01372 __d0 = __ll_lowpart (d); \ 01373 \ 01374 __r1 = (n1) % __d1; \ 01375 __q1 = (n1) / __d1; \ 01376 __m = (UWtype) __q1 * __d0; \ 01377 __r1 = __r1 * __ll_B | __ll_highpart (n0); \ 01378 if (__r1 < __m) \ 01379 { \ 01380 __q1--, __r1 += (d); \ 01381 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ 01382 if (__r1 < __m) \ 01383 __q1--, __r1 += (d); \ 01384 } \ 01385 __r1 -= __m; \ 01386 \ 01387 __r0 = __r1 % __d1; \ 01388 __q0 = __r1 / __d1; \ 01389 __m = (UWtype) __q0 * __d0; \ 01390 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ 01391 if (__r0 < __m) \ 01392 { \ 01393 __q0--, __r0 += (d); \ 01394 if (__r0 >= (d)) \ 01395 if (__r0 < __m) \ 01396 __q0--, __r0 += (d); \ 01397 } \ 01398 __r0 -= __m; \ 01399 \ 01400 (q) = (UWtype) __q1 * __ll_B | __q0; \ 01401 (r) = __r0; \ 01402 } while (0) 01403 01404 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through 01405 __udiv_w_sdiv (defined in libgcc or elsewhere). */ 01406 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd) 01407 #define udiv_qrnnd(q, r, nh, nl, d) \ 01408 do { \ 01409 USItype __r; \ 01410 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \ 01411 (r) = __r; \ 01412 } while (0) 01413 #endif 01414 01415 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */ 01416 #if !defined (udiv_qrnnd) 01417 #define UDIV_NEEDS_NORMALIZATION 1 01418 #define udiv_qrnnd __udiv_qrnnd_c 01419 #endif 01420 01421 #if !defined (count_leading_zeros) 01422 #define count_leading_zeros(count, x) \ 01423 do { \ 01424 UWtype __xr = (x); \ 01425 UWtype __a; \ 01426 \ 01427 if (W_TYPE_SIZE <= 32) \ 01428 { \ 01429 __a = __xr < ((UWtype)1<<2*__BITS4) \ 01430 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \ 01431 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ 01432 } \ 01433 else \ 01434 { \ 01435 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ 01436 if (((__xr >> __a) & 0xff) != 0) \ 01437 break; \ 01438 } \ 01439 \ 01440 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ 01441 } while (0) 01442 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE 01443 #endif 01444 01445 #if !defined (count_trailing_zeros) 01446 /* Define count_trailing_zeros using count_leading_zeros. The latter might be 01447 defined in asm, but if it is not, the C version above is good enough. */ 01448 #define count_trailing_zeros(count, x) \ 01449 do { \ 01450 UWtype __ctz_x = (x); \ 01451 UWtype __ctz_c; \ 01452 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ 01453 (count) = W_TYPE_SIZE - 1 - __ctz_c; \ 01454 } while (0) 01455 #endif 01456 01457 #ifndef UDIV_NEEDS_NORMALIZATION 01458 #define UDIV_NEEDS_NORMALIZATION 0 01459 #endif
1.7.6.1
